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dd-03201 32- or 96-channel discrete-to-digital interface rxd3 description the dd-03201 is a discrete-to-digital interface device. the inputs have been designed to handle 28 v/gnd, 28 v/open, and open/gnd signals. the device can also be configured as either a 32 triple-redundant or 96 non- redundant discrete input with either a microprocessor and/or arinc 429 output. the device can be hirf pro- tected by adding capacitors to the input resistor network. the device uses comparators in a triple-redundant configuration to take a consensus of the input state and raise a flag when there is no consen- sus. the devices microprocessor output is an addressable 8-bit or 16- bit tri-state port, which selects chan- nel data, status, bounce, built-in-self- test (bist) and major fault. all are compatible with ttl logic. applications the design specifically addresses redundancy, built-in self-test autono- my, fault isolation and tolerance at the chip level. in the 96-channel mode the device loses the capability of taking consen- sus of the input states as well as mis- match. these features are triple- redundant configuration specific. all other features are still available. these features, along with high-relia- bility and low cost, enable the device to serve a variety of interface require- ments in aerospace applications, including flight critical, essential and non-essential functions. the optional arinc 429 output port is particularly well-suited to data concentrator requirements. features ? universal inputs -configurable as 28 v/gnd open/gnd, 28 v/open input resistor usage ? built-in self-test ? soft failure reporting deferred maintenance higher mtbur ? optional arinc 429 output port discrete 32 or 96 32 only data mismatch bounce 32 or 96 ch 32/96 discrete input reference input discrete 32 or 96 inputs test matrix shift 3 h/l test matrix transfer processor and 3 fault bit 32 or 96 discrete address decoder discrete data en 32 or 96 enable lo enable hi arinc data en 5 5 tristate drivers 16 data bus data (8/16 bits) fault* fault processing circuitry fault 32 or 96 32 or 96 transfer fault discrete data transfer verifier dual redundant clock and control logic sel0 sel2 1 mhz sel1 reset* 8/16 bus enable* address (a5..a0) data transfer arinc verifier bit discrete fault transfer fault arinc fault data bus 16 tri-state enables arinc429 tri-state drivers ready 10us clock 80us clock arinc 429 xmitter arinc 429 output (ttl) arinc429 data rate arinc429 message rate note: (*) indicates active low. data ready 2 figure 1. dd -03201 block diagram ? 1993, 1999 data device corporation u.s. patent no. 5526288
2 what is a discrete? advisory circular (faa), airworthiness approval of traffic alert and collision avoidance systems (tcas ii) and mode s transponders, ac20-131, defines a discrete as a separate, complete and distinct signal. in many instances these signals are binary, on or off, 28 v-based signals; they are typically open/gnd, 28 v/open, or 28 v/gnd with very low bandwidth (dc to 200 hz). while on the surface the translation of these signals to ttl-lev- els compatible with digital avionics may seem simple, rtca do-160c power, lighting and high-intensity-radiated-fields (hirf) are complicating factors. add to that the desire to have a standardized, addressable, reliable interface and the challenge becomes apparent. todays systems address the interface with circuits tailored for each interface comprised of r-c input filters, divider networks, diode isolation and comparators. multichannel interface to a processor requires additional logic and latches. the resulting circuit generally lacks any built-in test capability, consumes con- siderable pc-board real estate (up to one sq. in. per channel), and offers no chip-level redundancy. functional integration using the aggregated definition and functional requirements of industry, ilc data device corporation has developed a pro- grammable 32/96-channel discrete interface with inputs capable of handling 28 v/open, open/gnd and 28 v/gnd signals. when using the 32-channel mode, the design uses comparators in a triple-redundant configuration, so that each channel will take a consensus of the input state, and raise a flag when there is no consensus (concensus fails).the devices output is a selectable 8-bit or 16-bit tri-state port, which can be addressed for channel data, status, bounce, built-in-self-test and major fault information. this design specifically addresses built-in self-test autonomy, fault isolation and tolerance; moreover, its functional integration 20.0 c/w q ca 5.0 c/w q jc junction temperature 210 c (body, 2 sec. duration) 280 c (localized, 1 sec. duration) lead temperature 150 -65 c storage temp 70 0 c n type 3 125 -55 c n type 2 85 -40 c n type 1 operating temperature thermal 250.0 125.0 mw p d power dissipation 45 25 ma (total v dd , analog & digital) i dd (v dd = +5v [digital outputs unloaded]) power supply requirements v dd v ss v input channel and corresponding reference input n input common mode range: 15 -15 mv input channel to corresponding reference input n input offset voltage: 1.0 -1.0 m a self-test inputs 1.0 -1.0 m a reference inputs 0.1 -0.1 m a input channels analog inputs analog inputs n input currents: 0.4 v n v ol (l ol = 4ma) v dd -0.5 v n v oh (i oh =-1ma) 2.4 v n v oh (l oh = 4ma) digital outputs 1.01 1.00 0.99 mhz clock inputs (see note 1) 0.8 v n v il 2.0 v n v ih digital inputs ttl logic compatibility inputs/outputs digital 5.5 4.5 v supply voltages (v dd ) operating conditions v dd +0.3 -0.3 v digital inputs v dd +0.3 -0.3 v analog inputs 7.0 5.0 -0.3 v supply voitages (v dd ) absolute maximum ratings max typ mln units parameter table 1. dd-03201 specification note: for the arinc 429 option the bit rate is derived from the clock. refer to arinc 429 bit rate to avoid interference. arinc 429-14 (january 4, 1993), paragraph 2.4,: timing related elements contains a commentary section following subparagraph 2.1.4.2 (low speed operation) that cautions against using precisely 100 kilobits per sec- ond. in. (mm) oz. (g) 96-channel: 269,326 hrs. 32-channel: 332,742 hrs. max typ mln units table 1. dd-03201 specification size weight physical characteristics 1.1 x 1.1 28 x 28 1.0 26.0 parameter mtbf per mil-hbk 217 for airborne inhabited cargo at 64c
3 results in significant added reliability. a comparative look at mtbf calculated in accordance with mil-hbk-217 for airborne inhabited cargo environments at 64c indicates an order of magnitude improvement for an integrated approach vs. a simi- larly packaged discrete-component implementation. moreover, the real estate is reduced from 32 square inches to 1.21 square inches for a 32-channel and from 64 square inches to 1.21 square inches for the 96-channel device. additional key features include: fault isolation: in 32-channel mode, triple-redundant com- parators are physically located on three different edges of the custom chip so that an edge failure is not catastrophic. fault tolerance: in 32-channel mode, a single comparator failure is reported as a mismatch or bit fault, but does not result in a hard-failure. bounce: relays and switches, as mechanical devices, have a characteristic bounce to their signal transition. it is desirable to mask this bounce by delaying the output digital transition accordingly. this sampling rate of the device can be varied to allow for debounce of relay/switch inputs. in addition, the triple sampling of a given comparator enables a consistent reading of otherwise asynchronous signals. bounce is an addressable reg- ister that allows the user to detect bouncing or intermittent relays/switches. registers: 8-bit or 16-bit selectable data or status is available via tri-state buffers for interface to any system processor. optional arinc 429 port: a serial arinc 429 output is avail- able for data concentrator applications. this enables the trans- fer of data to other systems with a minimum of wiring and processor loading. test patterns: internal test patterns can be selected to pro- duce alternating 1s and 0s to verify that all address and data bits are operational. these outputs are always available, regardless of ready state. they must be addressed by the user (a5... a0) in accordance with tables 3 and 4. dissimilar paths: errors are reported through registers and the optional arinc 429 port as crosschecks. deferred maintenance: the error reporting scheme differ- entiates soft- and hard-failures to allow continued operation despite failures. intelligence: the devices built-in self-test, status reporting scheme and fault-tolerance/isolation significantly reduces appli- cation software requirements. figure 1 illustrates the model dd-03201 functional block diagram. microprocessor interface read cycle timing the dd-03201 is configured with either an 8-bit or a 16-bit microprocessor. figure 2 illustrates this interface. the read cycle(s) should be preceded by polling the devices ready bit which is located within the status register. the status register can be read at any time regardless of the state of the ready signal (pin 150) from the device. if the ready bit is a logic 1 (this can be easily tested by a branch if negative statement) the address of the desired regis- ter, along with the negative true enable signal, should be pre- sented to the device. the additional data will be available with- in 100 nsec. after the data is read the enable line should be returned to a logic 1 level. all of the data within the device is guaranteed to remain stable for at least 20 sec after the high-to-low transition of the ready signal (see figure 3). analog inputs figure 4 illustrates the architecture of the analog input and front-end self-test circuits. each group of 32-channels (a, b and c groups) are identically configured, with ref_a setting the threshold for the a group of comparators, ref_b setting the threshold for the b group, etc. during the self-test portion of each cycle, the comparator inputs are switched from the nor- mal to the test position, an alternating 1/0 (hi/lo) pattern is applied to each group of comparators and a functional test is performed. the test is then repeated with an alternating 0/1 (lo/hi) pattern. input channels: (pins 4-19, 22-37, 44-59, 62-77, 81-96 and 99-114) configured as three groups of 32-channels each; each group is associated with its own reference and self-test inputs. the device may be connected as 96-independent chan- nels or 32-triple-redundant channels. refer to figure 5 and fig- ure 6 for a typical example of each configuration. for 32-chan- nel operation, channel 1 drives the a1, b1 and c1 inputs, channel 2 drives the a2, b2 and c2 inputs, and so forth. the example in figure 5 shows redundant input networks that pro- vide isolation between asic input pins and protect the two work- ing channel sections in the event of a short from an asic input pin to ground or v dd on the the third section. reference inputs: (pins 39, 79 and 116) each reference input sets the threshold voltage for the corresponding group of 32 comparators. self-test inputs: (pins 38, 40, 78, 80, 115 and 117) high and low self-test threshold settings. these settings should be set to at least 100 mv above (hi) and 100 mv below (lo) the reference (ref) input for the corresponding group of 32 comparators.
4 1mhz clock osc. cmos +5v chan1..32or1..96 ref a, b, c dd-03201 d15..d0 a5..a0 ready cpu enable 8/16*bits sel 2..0 the following must also be modified: then the dd-03201 is configured for 8-bit mode. 1) if 8/16* bits pin is tied to +5 volts, note: d0 tied to d8 d1 tied to d9 d2 tied to d10 d3 tied to d11 d4 tied to d12 d5 tied to d13 d6 tied to d14 d7 tied to d15 2) if the arinc 429 option is not used, then pin 156 (429strbi) must be grounded for the "bounce" circuit to operate properly. * indicates active low signal figure 2. dd-03201 to cpu interface ready address enable* data tra 10 ns min (see note 3) 10 ns min tea - 10 ns min 100 ns min tedoff 50 ns min ted tavail 20 s note: 1) tra = time ready address 2) tae = time address enable 3) tea = time enable to address 4) ted = time enable data 5) tedoff = time enable off - data off 6) tavail = time ready* - data available 7) (*) indicates active low. 8) the ready "on-time" = (sample rate - 440 s) sample rate is programmable via sel0 - sel2 (see table 2) tae figure 3. read cycle timing
5 - - - - - - + + + + + + 26 comparators and switches (b2 through b27) b1 test normal b28 b31 b32 b30 b29 44 73 74 75 76 77 78 79 80 test_b_hi ref_b test_b_lo comparators data_b_1 data_b_28 hlb lo lo hi hi data_b_29 data_b_30 data_b_31 data_b_32 test figure 4. dd-03201 (asic) input structure dd-03201 test c lo test c lo ref c c32 c2 c1 test b lo test b hi ref b b32 32/96 b2 a32 a2 a1 b1 channel 33 in channel 1in channel 2in channel 32 in channel 34 in channel 64 in channel 96 in channel 66 in channel 65 in ref b in ref c in ref a in test a lo ref a test a hi dd-03201 test c lo test c lo ref c c32 c2 c1 test_b_lo test_b_hi ref_b b32 32/96 vdd b2 a32 a2 a1 b1 channel 1in channel 2in channel 32 in ref in test a lo ref a test a hi figure 5. dd-03201 32-channel configuration figure 6. dd-03201 96-channel configuration
6 desired 8- or 16-bit data bus information in accordance with table 5 and table 6 (word/byte modes). clka and clkb (1mhz clk): (pins 160 and 121) dual redun- dant input clock paths are provided to the asic at two widely separated points to improve operational reliability. the 1 mhz clock should be connected to both clka and clkb inputs (exact frequency and stability is important only to the serial bit rate of the arinc 429 port, see note 1, table 1). optional isolation resistors (200 ohms maximum) may be installed in series with each input to facilitate testing of the clock monitoring circuitry (see figure 7). in the event of loss of clka (primary) input to asic, internal circuitry combined with external rc net- works (see a timer and b timer ) switches to the clkb (sec- ondary) source. both clocks are continuously monitored for sta- tus and this information is available as separated bits in the status register. a timer and b timer: (pins 124 and 123) clock monitoring and switching depends upon rc networks installed at these two pins (figure 7). each pin must have a 100 k w , 5% resistor to vdd and a 0.001 f, 20% capacitor to ground. factory test inputs: (pins 41, 42, 152 and 153) the tmux, tmode, fmux and fmode input signals are used for factory testing and should be tied to logic 1 for the device to operate properly. reset: (pin 43) the reset signal is used to reset the device during factory testing. it must be connected to an external rc network (100 k w, 5% resistor to v dd and a 0.01f, 20% capaci- tor to ground) to provide a power-on-reset for the device. if there is some reason to reset the device from external circuitry this pin can be momentarily pulled to logic 0 through an open collector device. do not hard wire this pin to +5v or ground. digital inputs debounce (sel2...sel0): (pins 1-3) the input discrete sampling rate (debounce time) is user-programmable via the three select lines (sel2...sel0) in accordance with table 2. the intent of this function is to mask the bounce of the input dis- crete appropriate to its characteristic performance. see bounce on page 3. enable: (pin 149) the enable line controls the tri-state dri- vers of the 8- or 16-bit data bus outputs. the tri-state data bus drivers are enabled when this signal is a logic 0, and are tri- stated when this signal is a logic 1. enable is a read signal and should only be low during read cycles. 8 /16 bits: (pin 119) a logic 0 selects the 16-bit data bus out- put and logic 1 selects the 8-bit data bus output. address lines (a5...a0): (pins 143-148) the six address lines (a5... a0, where a0 is the lsb) provide for the selection of the figure 7. dd-03201 clock inputs and timers clkb clka 1 mhz clock b timer a timer vdd vdd asic table 2. discrete sampling rate select (sel 2 . . sel 0) sample rate 000 5 msec 001 10 msec 010 20 msec 011 50 msec 100 100 msec 101 200 msec 110 500 msec 111 1000 msec
7 see notes at left. notes for tables 3 and 4. note 5: a data bit indicates the triple-redundant vote or unanimous consensus of the input discrete state for the associated channel over the last two data samples taken. note 4: a fault bit that is true indicates that the associated channel has a major problem and the associated data should not be believed. a fault is a hard fault condition. note 3: a bit indication for any channel signifies that the associated channel has failed the built-ln-test sequence which is performed prior to every input sample taken. these signals are reset at the start of each built-ln-test sequence, and will be set if any of the tests in the sequence fail. a bit indication is a hard fault condition indicating that the built-in-test has failed one or more of the voltage tests. note 2: a mismatch bit that is true indicates that one of the triple- redundant inputs of the associated channel did not agree with the other two for three consecutive samples of the input i.e., there was a lack of consensus for the three inputs. a mismatch indication is a soft fault condition indicating that there is a problem with the channel but the associated output data can be believed because of the internal voting taking place. note 1: a true bounce bit indicates that the input signal of the associat- ed channel changed in an alternating fashion, i.e., off-on-off or on- off-on in three successive samples at the selected sampled rate. not used 11 1111 : 10 1101 not used 10 1100 test pattern 1s and 0s 10 1011 test pattern 1s and 0s 10 1010 not used 10 1001 not used 10 1000 not used 10 0111 not used 10 0110 not used 10 0101 not used 10 0100 not used 10 0011 not used 10 0010 not used 10 0001 not used 10 0000 factory test word 4 hl 01 1111 factory test word 4 lo 01 1110 factory test word 3 hl 01 1101 factory test word 3 lo 01 1100 factory test word 2 hl 01 1011 factory test word 2 lo 01 1010 factory test word 1 hl 01 1001 factory test word 1 lo 01 1000 status register hl 01 0111 status register lo 01 0110 test pattern 0s and 1s 01 0100 test pattern 0s and 1s 01 0100 data ch_32 ch_25 01 0011 data ch_24 ch_17 01 0010 data ch_16 ch_09 01 0001 data ch_08 ch_01 01 0000 fault ch_32 ch_25 00 1111 fault ch_24 ch_17 00 1110 fault ch_1 6 ch_09 00 1101 fault ch_08 ch_01 00 1100 bit ch_32 ch_25 00 1011 bit ch_24 ch_17 00 1010 bit ch_16 ch 09 00 1001 bit ch_08 ch_01 00 1000 mismatch ch_32 ch_25 00 0111 mismatch ch_24 ch_17 00 0110 mismatch ch_1 6 ch_09 00 0101 mismatch ch_08 ch_01 00 0100 bounce ch 32 ch 25 00 0011 bounce ch_24 ch_17 00 0010 bounce ch_1 6 ch_09 00 0001 bounce ch_08 ch_01 00 0000 data (d7...d0) address (a5...a0) table 4. 32-channel byte mode (8-bit bus) address (a5...a0) data (d7...d0) 00 000x bounce ch 16..ch_01 00 001x bounce ch 32..ch 17 00 010x mismatch ch_16..ch_01 00 011x mismatch ch_32..ch 17 00 100x bit ch_16..ch_01 00 101x bit ch 32 ch_17 00 110x fault ch_1 6 ch 01 00 111x fault ch_32 ch 17 01 000x data ch 1 6 ch_01 01 001x data ch 32 ch_17 01 010x test pattern 0s and 1s 01 011x status register 01 100x factory test word 1 01 101x factory test word 2 01 110x factory test word 3 01 111x factory test word 4 10 000x not used 10 001x not used 10 010x not used 10 011x not used 10 100x not used 10 101x test pattern 1s and 0s 10 110x not used 10 111x : 11 111x not used table 3. 32-channel word mode (16-bit bus) note 6: the two available test patterns contain an alternating string of 1s and 0s, and 0s and 1s, which can be used to verify that all of the data bits are operational, i.e., there are no stuck bits. the two test patterns have been located at addresses of alternating address bits so that the address decoder bits are tested at the same time.
8 see notes at left. test word 2 lo 10 1110 test word 1 hl 10 1101 test word 1 lo 10 1100 test pattern 1s and 0s 10 1011 test pattern 1s and 0s 10 1010 status register hl 10 1001 status register lo 10 1000 not used 10 0111 not used 10 0110 data ch_96..ch_89 00 1010 data ch_88..ch_81 10 0100 data ch_80..ch_73 10 0011 data ch_72..ch_65 10 0010 data ch_64..ch_57 10 0001 data ch_56..ch_49 10 0000 data ch_48..ch_41 01 1111 data ch_40..ch_33 01 1110 data ch_32..ch_25 01 1101 data ch_24..ch_17 01 1100 data ch_16..ch_09 01 1011 data ch_08..ch_01 01 1010 fault ch_96..ch_89 01 1001 fault ch_88..ch_81 01 1000 fault ch_80..ch_74 01 0111 fault ch_73..ch_65 01 0110 test pattern 0s and 1s 01 0101 test pattern 0s and 1s 01 0100 fault ch_64..ch_57 01 0011 fault ch_56..ch_49 01 0010 fault ch_48..ch_41 01 0001 fault ch_40..ch_33 01 0000 fault ch_32..ch_25 00 1111 fault ch_24..ch_17 00 1110 fault ch_16 ch_09 00 1101 fault ch_08..ch_01 00 110.0 bounce 96 ch_89 00 1011 bounce 88..ch_81 00 1010 bounce 80 ch_74 00 1001 bounce 73..ch_65 00 1000 bounce_64 ch_57 00 0111 bounce_56..ch_49 00 0110 bounce_48 ch_41 00 0101 bounce ch_40..ch_33 00 0100 bounce ch_32..ch_25 00 0011 bounce ch_24..ch_17 00 0010 bounce ch_16..ch_09 00 0001 bounce ch_08..ch_01 00 0000 data (d7...d0) address (a5...a0) table 6. 96-channel byte mode (8-bit bus) note 4: the two available test patterns contain an alter- nating string of 1s and 0s and 0s and 1s, which can be used to verify that all of the data bits are operational, i.e., there are no stuck bits. the two test patterns have been located at address- es of alternating address bits so that the address decoder bits are tested at the same time. note 3: a data bit indicates the input discrete state for the associated channel over two out of the last three samples taken. note 2: a fault bit that is true indicates that the associated channel has a major problem and the associated data should not be believed. a fault indication is a hard fault condition. note 1: a true bounce bit indicates that the input signal of the associated channel changed in an alternating fashion i.e. off-on-off or on-off-on in three consecutive samples at the selected sample rate. notes for tables 5 and 6: not used 11 111x : 11 011x not used 11 010x factory test word 4 11 001x factory test word 3 11 000x factory test word 2 10 111x factory test word 1 10 110x test pattern 1s and 0s 10 101x status register 10 100x not used 10 011x data ch_96..ch_81 10 010x data ch_80..ch_65 10 001x data ch_64..ch_49 10 000x data ch_48..ch_33 01 111x data ch_32..ch_17 01 110x data ch_16..ch_01 01 101x fault ch_96..ch_81 01 100x fault ch_80..ch_65 01 011x test pattern 0s and 1s 01 010x fault ch_64..ch_49 01 001x fault ch_48..ch_33 01 000x fault ch_32..ch_17 00 111x fault ch_16..ch_01 00 110x bounce ch_96..ch_81 00 101x bounce ch_80..ch_65 00 100x bounce ch_64..ch_49 00 011x bounce ch_48..ch_33 00 010x bounce ch_32..ch_17 00 001x bounce ch_16..ch_01 00 000x data (d7...d0) address (a5...a0) table 5. 96-channel word mode (16-bit bus)
9 outputs data (d15...d0): (pins 125-140) 8-bit byte or 16-bit byte word information is available on the data bus depending on the logic state of the bus select line as described above. in the byte mode the upper and lower bytes are enabled separately so that bit 0 can be hard wired to bit 8, bit 1 to bit 9 etc., thereby pro- viding an 8-bit data bus. it is important that the 8-bit mode be selected if these data bits are wired together, otherwise corrupted data will result. the available data can be found under address lines (a5...a0) . fault: (pin 151) the fault flag was designed to serve as an interrupt to the microprocessor when a hard or soft error has been detected within the device (see bit and fault notes in table 4). if this signal is asserted (logic 0) the status register should be read to determine the nature of the fault. thereafter more detailed information can be found in the asso- ciated addressable registers. the fault flag will remain at a logic 0 for as long as the fault condition persists. figure 8 and figure 9 illustrate the fault logic tree for the 32-channel and the 96-channel respectively. note: depending on the exact nature of the fault, the fault flag may return to logic 0 during the built-in-test interval (when the ready signal is at logic 0) if there is a persistent fault condition. fault conditions: fault is logic 0 for any of the following fault conditions. the reason for the fault can be obtained from the status register which is accessible regardless of ready state. table 7 shows the contents of the status register. a definition of each bit is as follows: bit fault: a logic 1 for this bit indicates that one of the chan- nels has failed the built-in-test sequence. the offending chan- nel(s) can be determined by reading the associated bit data words. discrete fault: a logic 1 for this bit indicates that one of the channels detected a hard failure during the built-in-test sequence, or that the discrete input data word did not transfer to the data bus output properly when it was read. if a hard fault was detected the offending channel can be determined by read- ing the associated fault data registers. if it was generated by a transfer error the discrete transfer fault bit in this status register will be set to logic 1. arinc fault: a logic 1 for this bit indicates that one of the channels detected a hard failure during built-in-test sequence, or that the discrete input word did not transfer to the arinc transmitter section properly. if a hard fault was detected the offending channel can be determined by reading the associated fault data registers. if it was generated by a transfer error then no fault bits will be set to logic 1.? arinc ready: a logic 0 for this bit indicates that an arinc transmission is currently in progress. a logic 1 indicates that no arinc transmission is in progress.? clock_a fault: a logic 1 for this bit indicates that the pri- mary 1 mhz clock is currently defective and that the device is running off the secondary 1 mhz clock. ? clock_b fault: a logic 1 for this bit indicates that the sec- ondary 1 mhz clock is currently defective and cannot be used as a backup. no clock: a logic 1 for this bit indicates that there is no 1 mhz clock being supplied to the device (or that both have failed). discrete transfer fault: a logic 1 for this bit indicates that the discrete data word(s) did not transfer properly during the associated microprocessor read cycle, i.e., the word present on the data bus did not agree with internal data. the most likely cause of this type of fault condition is a collision on the data bus during the read cycle. note: this condition is only monitored for the discrete data words, not for all of the available data. ready: (pin 150) a logic 1 for this bit indicates that all of the available data is stable and can be read. a logic 0 indicates that the device is in built-in-test mode, or taking a sample of discrete input data lines. the signal should be polled directly by reading the status word prior to performing any read cycles. the internal data is guaran- teed to be stable for 20 sec after the logic 1 to logic 0 tran- sition (ready to not ready) of this signal. therefore, it should not be necessary to repoll the signal after the read. ? this signal is only meaningful for the arinc 429 device option. note: all bits available regardless of ready-state. table 7. status register word bit map bit signal 00 bit fault 01 discrete fault 02 arinc fault 03 arinc ready 04 clock_a fault 05 clock_b fault 06 no clock 07 discrete transfer fault 08 logic low (high byte) 09 logic low 10 logic low 11 logic low 12 logic low 13 logic low 14 logic low 15 ready
10 discrete transfer fault no clock (status reg) (status reg) q (status reg) discrete fault r s 1 2 3 1 2 3 / / 32 matrix circuit fault bounce bit fail / / 32 2 3 1 fault* / / / / 32 32 2 3 1 1 2 3 not in bit mis- match clock a missing clock b missing (status reg) (status reg) 1 2 3 3 r s q bit fault (status reg) read status clear strobe 1 2 (pin 99) discrete transfer fault no clock (status reg) (status reg) q (status reg) discrete fault r s 1 2 3 1 2 3 / / 96 matrix circuit fault bounce bit fail / / 96 2 3 1 fault* / / 96 clock a missing clock b missing (status reg) (status reg) 1 2 3 3 r s q bit fault (status reg) read status clear strobe 1 2 (pin 99) figure 8. 32-channel fault logic tree figure 9. 96-channel fault logic tree note: (*) indicates active low. note: (*) indicates active low.
11 arinc 429 port (optional) dd-03201xx-xx4 indicates the inclusion of the arinc 429 data output. this option enables the transmission of discrete data via serial arinc 429 (cmos levels) output lines. the fol- lowing features and pins apply: arinc 429 data rate (429drate): (pin 159) a logic 1 (or a no-connect) for this input selects the arinc 429 low speed data rate of 12.5 khz. a logic 0 selects the high speed data rate of 100 khz.? arinc 429 message rate (429mrate): (pin 158) the mes- sage rate of the arinc output is selectable at either a fixed 100 msec rate or at the selected sampling rate of the input discretes. a logic 1 selects the input sampling rate as the message rate, and a logic 0 selects the fixed 100 msec message rate. note: if the low-speed arinc 429 bit rate is selected (12.5k bps) an entire arinc message will take about 35 msec to complete. therefore, input discrete sampling rates of 5 msec, 10 msec, and 20 msec cannot be utilized or the arinc mes- sage will be truncated unless the fixed 100 msec message rate is selected. 429 strobe in (429strbi): (pin 156) this pin is utilized in the special case where the device is being used as a remote arinc 429 serial port and is not connected to a local microprocessor. when the device is being used in this specific configuration the associated 429 strobe out should be connected to this pin. in other cases this pin must be grounded. related information: because the bounce data is momentary, it is latched within the device. this information is normally reset by a read to the associated bounce data words. in the instance where there is no microprocessor, and therefore no reads to the bounce data, this connection provides a mech- anism to reset the source of the bounce information (just after it is transferred to the arinc transmitter section) at the start of each arinc message.? 429 strobe out (429strbo): (pin 157) this signal is used in conjunction with the 429 strobe in described in the preceding paragraph. it is a 500 nsec positive pulse which occurs at the start of each 429 message. for further information concerning the use of this signal see 429 strobe in (429strbi).? arinc_lo and arinc_hi: (pin 154 and 155) these two signals comprise the arinc 429 serial output transmission. both are ttl compatible signals where the arinc_lo signal contains the logic 0 serial transmission and the arinc_hi signal con- tains the logic 1 serial transmission. these two signals must be connected to a differential arinc 429 transmission signal. fig- ure 10 illustrates this interface. the content and word order of the arinc 429 transmission is shown in table 8 (32-channel) and table 9 (96-channel).? as noted, these features are only guaranteed and tested if the arinc 429 option is selected. in addition, the clock frequency (1 mhz) must be selected carefully so as not to interfere with other avionic communications as detailed in arinc 429. the arinc 429 option bit rate is derived from the (1 mhz) clock. refer to arinc 429 bit rate to avoid interference. arinc 429- 14 (january 4, 1993), paragraph 2.4 timing related elements contains a commentary section following subparagraph 2.1.4.2 (low speed operation) that cautions against using precisely 100 kilobits per second. optional 429 line driver if you choose the 429 option for the dd-03201, you can use a line driver chip to transmit the data on the serial data bus. ddc has such a device, the dd-03182 which will support arinc 429, 571, and 575 bus standards. see figure 10 for connec- tion diagram. chan 1..96 ref a, b, c sel 2..0 1 mhz clock osc. dd-03201 dd-03182 429 line- driver arinc arinc hi arinc lo +5v note: 1) 429 mrate and drate can either be tied to gnd or +5v (refer to page 11) 2) if the arinc 429 option is not used, then pin 153 (429strbi) must be grounded for the "bounce" circuit to operate properly. +15v -15v 429drate 429mrate 429strbo 429strbi figure 10. dd-03201 to arinc 429 interface ? this signal is only significant for the arinc 429 device option.
12 notes: ab = 00, if there are no major faults. ab = 11, if major faults exsist (data is bad). c = 0, when 429 data rate is 100 kbps; c = 1 when data rate is 12.5 kbps. d = data bit. f = 1, if the discrete interface output has any major faults (429 data may still be good). p = arinc 429 parity bit e = 1, if there is a bit fault. gh = the value of these two locations will track channel 1 and 2, or can be hard-wired (via channel 1 and 2) to determine which rxd3 the 429 word came from. the 12 words are transmitted in order shown from top to bottom. table 8. 32-channel arinc bit description arnc 429 bts 32 31 ssm 30 29 msb 28 27 26 25 24 23 16 bit data 22 21 20 19 18 17 16 15 lsb 14 13 f 12 c 11 10 sdi 9 label reversed octal l s b 8 7 6 5 4 3 2 m s b 1 triple bounce 16..1 p a b d d d d d d d d d d d d d d d d e f c g h 1 0 0 0 0 0 0 0 001 triple bounce 32..17 p a b d d d d d d d d d d d d d d d d e f c g h 0 1 0 0 0 0 0 0 002 mismatch 16..1 p a b d d d d d d d d d d d d d d d d e f c g h 1 1 0 0 0 0 0 0 003 mismatch 32..17 p a b d d d d d d d d d d d d d d d d e f c g h 0 0 1 0 0 0 0 0 004 bit 16..1 p a b d d d d d d d d d d d d d d d d e f c g h 1 0 1 0 0 0 0 0 005 bit 32..17 p a b d d d d d d d d d d d d d d d d e f c g h 0 1 1 0 0 0 0 0 006 triple fault 16..1 p a b d d d d d d d d d d d d d d d d e f c g h 1 1 1 0 0 0 0 0 007 triple fault 32..17 p a b d d d d d d d d d d d d d d d d e f c g h 0 0 0 1 0 0 0 0 010 triple data 16..1 p a b d d d d d d d d d d d d d d d d e f c g h 1 0 0 1 0 0 0 0 011 triple data 32..17 p a b d d d d d d d d d d d d d d d d e f c g h 0 1 0 1 0 0 0 0 012 test 5s p 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 e f c g h 1 1 0 1 0 0 0 0 013 test as p 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 e f c g h 0 0 1 1 0 0 0 0 014 p a r
13 notes: ab = 00, if there are no major faults. ab = 11, if major faults exsist (data is bad). c = 0, when 429 data rate is 100 kbps; c = 1 when data rate is 12.5 kbps. d = data bit. f = 1, if the discrete interface output has any major faults (429 data may still be good). p = arinc 429 parity bit e = 1, if there is a bit fault. gh = the value of these two locations will track channel 1 and 2, or can be hard-wired (via channel 1 and 2) to determine which rxd3 the 429 word came from. the 20 words are transmitted in order shown from top to bottom. label reversed octal l s b sdi c f l s b m s b 16 bit data m s b ssm p a r 024 023 022 021 020 017 016 015 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 h h h h h h h h g g g g g g g g c c c c c c c c f f f f f f f f e e e e e e e e d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d b b b b b b b b a a a a a a a a p p p p p p p p data 96..81 data 80..65 data 64..49 data 48..33 data 32..17 data 16..1 bounce 96..81 bounce 80..65 014 0 0 0 0 1 1 0 0 h g c f e 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 p test as 013 0 0 0 0 1 0 1 1 h g c f e 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 p test 5s 012 011 010 007 006 005 004 003 002 001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 h h h h h h h h h h g g g g g g g g g g c c c c c c c c c c f f f f f f f f f f e e e e e e e e e e d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d b b b b b b b b b b a a a a a a a a a a p p p p p p p p p p bounce 64..49 bounce 48..33 bounce 32..17 bounce 16..1 fault 96..81 fault 80..65 fault 64..49 fault 48..33 fault 32..17 fault 16..1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 arinc 429 bts table 9. 96-channel arinc bit description
14 notes: 1. refer to analog inputs section and figures 4, 5 and 6. 2. refer to a timer and b timer section and figure 7. 3. (*) indicates an active low signal. 4. analog v dd input. 5. digital v dd input. 6. analog gnd. 7. digital gnd. 8. analog v dd and digital v dd inputs must be tied to the same local supply potential. 9. analog gnd and digital gnd inputs must be tied to the same local ground potential. 10.(**) refer to clka and clkb section and figure 7. table 10. dd-03201 pin functions function pin number function pin number function 1 sel0 55 ch44 109 ch70 2 sel1 56 ch45 110 ch69 3 sel2 57 ch46 111 ch68 4 ch1 58 ch47 112 ch67 5 ch2 59 ch48 113 ch66 6 ch3 60 v dd b (note 4, 8) 114 ch65 7 ch4 61 vss2 (note 6, 9) 115 test c hi (note 1) 8 ch5 62 ch49 116 ref c (note 1) 9 ch6 63 ch50 117 test c lo (note 1) 10 ch7 64 ch51 118 v dd (note 5, 8) 11 ch8 65 ch52 119 bits 8/16* 12 ch9 66 ch53 120 ch32/96* 13 ch10 67 ch54 121 clkb (1mhz clk)** 14 ch11 68 ch55 122 vss (note 7, 9) 15 ch12 69 ch56 123 b timer (note 2) 16 ch13 70 ch57 124 a timer (note 2) 17 ch14 71 ch58 125 d15 18 ch15 72 ch59 126 d14 19 ch16 73 ch60 127 d13 20 v dd a (note 4, 8) 74 ch61 128 d12 21 vss1 (note 6, 9) 75 ch62 129 d11 22 ch17 76 ch63 130 d10 23 ch18 77 ch64 131 d9 24 ch19 78 test b hi (note 1) 132 d8 25 ch20 79 ref b (note 1) 133 d7 26 ch21 80 test b lo (note 1) 134 d6 27 ch22 81 ch96 135 d5 28 ch23 82 ch95 136 d4 29 ch24 83 ch94 137 d3 30 ch25 84 ch93 138 d2 31 ch26 85 ch92 139 d1 32 ch27 86 ch91 140 d0 33 ch28 87 ch90 141 vssdig (note 7, 9) 34 ch29 88 ch89 142 v dd dig (note 5, 8) 35 ch30 89 ch88 143 addr5 36 ch31 90 ch87 144 addr4 37 ch32 91 ch86 145 addr3 38 test a hi (note 1) 92 ch85 146 addr2 39 ref a (note 1) 93 ch84 147 addr1 40 test a lo (note 1) 94 ch83 148 addr0 41 tmode* 95 ch82 149 enable* 42 tmux* 96 ch81 150 ready 43 reset* 97 v dd c (note 4, 8) 151 fault* 44 ch33 98 vss3 (note 6, 9) 152 fmux* 45 ch34 99 ch80 153 fmode* 46 ch35 100 ch79 154 arinc lo 47 ch36 101 ch78 155 arinc hi 48 ch37 102 ch77 156 429strbi 49 ch38 103 ch76 157 429strbo 50 ch39 104 ch75 158 429mrate 51 ch40 105 ch74 159 429drate 52 ch41 106 ch73 160 clka (1mhz clk)** 54 53 ch43 ch42 108 107 ch71 ch72 pin number
15 figure 11. dd-03201 mechanical outline (ceramic package) 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 pin no. 1 index 1 160 120 121 81 80 41 40 pin numbers for ref. only 0.0256 (.65) (typ) 1.102 0.011 (27.99 0.28 ) 1.102 0.011 (27.99 0.28 ) 0.103 (2.61) 0.077(1.96) (typ) see detail "a" 1.194 (30.3) (ref) 0.031(0.79) (typ) 0.085 0.009 (2.159 0.23 ) 1.256 0.01 (31.9) (typ) 0.012 +0.002 -0.001 ( 0.3 +0.05 ) -0.03 (typ) detail "a" nts 0.040(1.01) (typ) 0.046(1.17) (ref) 0.006 +0.002 -0.001 ( 0.15 +0.05 ) -0.03 (typ) 0.008 0.003 (0.18 0.08 ) (typ) 0.025 x 45 deg. (0.64 x 45 deg. ) chamfer (4 plcs) notes: 1 lead cluster to be centralized about case centerline within 0.010 (0.25). 2. dimensions in inches (millimeters). top view
16 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 pin no. 1 index 1 160 120 121 81 80 41 40 pin numbers for ref. only 0.0256 (.65) (typ) detail "a" nts 0.016 (0.41) (min) (typ) 0.031(.79) (typ) 0.007 0.002 (0.18) (typ) 0.133 (3.38) (ref) 0.077(1.96) (typ) 1.256 0.01 (31.9) (typ) see detail "a" 0.146 +0.008 (3.71) -0.000 0.013 +0.000 (0.33) -0.003 0.012 0.003 (0.3 0.08 ) (typ) 1.102 0.004 (27.99 0.1 ) 1.102 0.004 (27.99 0.1 ) notes: 1 lead cluster to be centralized about case centerline within 0.010 (0.25). 2. dimensions in inches (millimeters). figure 12. dd-03201 mechanical outline (plastic package) top view
17 ordering information dd-03201fc-110 arinc port option: 0 = without arinc 429 output 4 = with arinc 429 output screening: 0 = standard ddc procedures temperature range: 1 = -55c to + 125c ( ceramic only) 2 = -40c to + 85c asic package type: p = plastic c = ceramic package style: f = surface mount other applicable documents rtca/do-160c: environmental conditions and test procedures for airborne equipment. optional hardware dd-03182xx-xxxx C arinc 429 line driver t = tape and reel (gp and vp only) options: 0 = with resistors and fuses 1 = with resistors, no fuses* screening: 0 = standard ddc procedures 2 = burn-in (ceramic only) temperature range: 1 = -55 to +125c (ceramic only) 2 = -40 to +85c 9 = -55 to +85c (gp package only) package style/type: dc = 16-pin ceramic dip gp = 16-pin plastic soic pp = 28-pin plastic plcc vp = 14-pin plastic soic *vp version only.
18 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. d-06/98-1m printed in the u.s.a. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7402 headquarters - tel: (631) 567-5600 ext. 7402, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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